Abstract:
Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicron
integrated circuits. Small delay variations induced by crosstalk,
process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay
defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect
pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational
complexity and it excites a larger number of long paths compared to a commercial timing-aware ATPG tool. Our results also show
that, for the same pattern count, the selected patterns provide more
effective coverage ramp-up than timing-aware ATPG and a recent pattern-selection method for random small-delay defects potentially
caused by resistive shorts, resistive opens, and process variations.
