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dc.contributor.author Yilmaz, M
dc.contributor.author Chakrabarty, K
dc.contributor.author Tehranipoor, M
dc.date.accessioned 2009-09-14T13:20:52Z
dc.date.issued 2010-05
dc.identifier http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=000278502500009&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=47d3190e77e5a3a53558812f597b0b92
dc.identifier.citation IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2010, 29 (5), pp. 760 - 773
dc.identifier.issn 0278-0070
dc.identifier.uri http://hdl.handle.net/10161/1376
dc.format.extent 760 - 773
dc.format.mimetype application/pdf
dc.language.iso en_US en_US
dc.relation.ispartof IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
dc.relation.ispartofseries ECE-2009-02 en_US
dc.relation.isversionof 10.1109/TCAD.2010.2043591
dc.subject Delay test
dc.subject output deviations
dc.subject process variations
dc.subject small-delay defects
dc.subject test-pattern grading
dc.title Test-Pattern Selection for Screening Small-Delay Defects in Very-Deep Submicrometer Integrated Circuits
dc.type Journal Article
dc.department Engineering
pubs.author-url http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=000278502500009&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=47d3190e77e5a3a53558812f597b0b92
pubs.issue 5
pubs.organisational-group /Duke
pubs.organisational-group /Duke/Pratt School of Engineering
pubs.organisational-group /Duke/Pratt School of Engineering/Electrical and Computer Engineering
pubs.organisational-group /Duke/Trinity College of Arts & Sciences
pubs.organisational-group /Duke/Trinity College of Arts & Sciences/Computer Science
pubs.publication-status Published
pubs.volume 29

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