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dc.contributor.author Yilmaz, M
dc.contributor.author Chakrabarty, K
dc.contributor.author Tehranipoor, M
dc.date.accessioned 2009-09-14T13:20:52Z
dc.date.issued 2010-05-01
dc.identifier.citation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29 (5), pp. 760 - 773
dc.identifier.issn 0278-0070
dc.identifier.uri http://hdl.handle.net/10161/1376
dc.description.abstract Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and excites a larger number of long paths compared to a current generation commercial timing-aware ATPG tool. Our results also show that, for the same pattern count, the selected patterns provide more effective coverage ramp-up than timing-aware ATPG and a recent pattern-selection method for random SDDs potentially caused by resistive shorts, resistive opens, and process variations. © 2010 IEEE.
dc.format.extent 760 - 773
dc.format.mimetype application/pdf
dc.language.iso en_US en_US
dc.relation.ispartof IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
dc.relation.ispartofseries ECE-2009-02 en_US
dc.relation.isversionof 10.1109/TCAD.2010.2043591
dc.title Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits
dc.type Journal Article
dc.department Engineering
pubs.issue 5
pubs.organisational-group /Duke
pubs.organisational-group /Duke/Pratt School of Engineering
pubs.organisational-group /Duke/Pratt School of Engineering/Electrical and Computer Engineering
pubs.organisational-group /Duke/Trinity College of Arts & Sciences
pubs.organisational-group /Duke/Trinity College of Arts & Sciences/Computer Science
pubs.publication-status Published
pubs.volume 29

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