Abstract:
Timing-related defects are a major cause for test escapes and field returns for very-deep-sub-micron (VDSM) integrated circuits (ICs). Small-delay variations induced by crosstalk, process variations, power-supply noise, and
resistive opens and shorts can cause timing failures in a design, thereby leading to quality and reliability concerns.
We present the industrial application and case study of a previously proposed test-grading technique that uses the
method of output deviations for screening small-delay defects (SDDs). The technique is shown to have significantly lower computational complexity and test pattern count, without loss of test quality, compared to a commercial
timing-aware automatic test pattern generation (ATPG) tool.
