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dc.contributor.author Yilmaz, Mahmut
dc.contributor.author Chakrabarty, Krishnendu
dc.contributor.author Tehranipoor, Mohammad
dc.date.accessioned 2010-03-29T18:14:41Z
dc.date.available 2010-03-29T18:14:41Z
dc.date.issued 2010-03-29T18:14:41Z
dc.identifier.uri http://hdl.handle.net/10161/2137
dc.description.abstract Timing-related defects are a major cause for test escapes and field returns for very-deep-sub-micron (VDSM) integrated circuits (ICs). Small-delay variations induced by crosstalk, process variations, power-supply noise, and resistive opens and shorts can cause timing failures in a design, thereby leading to quality and reliability concerns. We present the industrial application and case study of a previously proposed test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). The technique is shown to have significantly lower computational complexity and test pattern count, without loss of test quality, compared to a commercial timing-aware automatic test pattern generation (ATPG) tool. en_US
dc.format.extent 483257 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US en_US
dc.relation.ispartofseries ECE-2010-01 en_US
dc.subject delay test en_US
dc.subject output deviations en_US
dc.title Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits en_US
dc.type Technical Report en_US
dc.department Engineering

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