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dc.contributor.author Zhang, M
dc.contributor.author Lebeck, AR
dc.contributor.author Sorin, DJ
dc.date.accessioned 2011-05-18T01:53:50Z
dc.date.issued 2010
dc.identifier http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=000288082400006&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=47d3190e77e5a3a53558812f597b0b92
dc.identifier.citation IEEE COMPUTER ARCHITECTURE LETTERS, 2010, 9 (2), pp. 61 - 64
dc.identifier.issn 1556-6056
dc.identifier.uri http://hdl.handle.net/10161/3764
dc.format.extent 61 - 64
dc.language.iso en_US en_US
dc.relation.ispartof IEEE COMPUTER ARCHITECTURE LETTERS
dc.relation.isversionof 10.1109/L-CA.2010.18
dc.subject Memory Consistency
dc.subject Multicore
dc.subject Verification
dc.subject Validation
dc.title Fractal Consistency: Architecting the Memory System to Facilitate Verification
dc.type Journal Article
duke.contributor.id 114435 en_US
pubs.author-url http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=000288082400006&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=47d3190e77e5a3a53558812f597b0b92
pubs.issue 2
pubs.organisational-group /Duke
pubs.organisational-group /Duke/Pratt School of Engineering
pubs.organisational-group /Duke/Pratt School of Engineering/Electrical and Computer Engineering
pubs.organisational-group /Duke/Trinity College of Arts & Sciences
pubs.organisational-group /Duke/Trinity College of Arts & Sciences/Computer Science
pubs.publication-status Published
pubs.volume 9

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