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dc.contributor.author Pistol, C
dc.contributor.author Chongchitmate, W
dc.contributor.author Dwyer, C
dc.contributor.author Lebeck, AR
dc.date.accessioned 2011-05-18T01:58:00Z
dc.date.issued 2010-01-01
dc.identifier.citation IEEE Micro, 2010, 30 (1), pp. 110 - 120
dc.identifier.issn 0272-1732
dc.identifier.uri http://hdl.handle.net/10161/3766
dc.description.abstract The authors explore nanoscale sensor processor (nSP) architectures. Their design includes a simple accumulator-based instruction-set architecture, sensors, limited memory, and instruction-fused sensing. Using nSP technology based on optical resonance energy transfer logic helps them decrease the design's size; their smallest design is about the size of the largest-known virus. © 2006 IEEE.
dc.format.extent 110 - 120
dc.language.iso en_US en_US
dc.relation.ispartof IEEE Micro
dc.relation.isversionof 10.1109/MM.2010.9
dc.title Architectural implications of nanoscale-integrated sensing and computing
dc.type Journal Article
duke.contributor.id 114435 en_US
pubs.issue 1
pubs.organisational-group /Duke
pubs.organisational-group /Duke/Pratt School of Engineering
pubs.organisational-group /Duke/Pratt School of Engineering/Electrical and Computer Engineering
pubs.organisational-group /Duke/Trinity College of Arts & Sciences
pubs.organisational-group /Duke/Trinity College of Arts & Sciences/Computer Science
pubs.publication-status Published
pubs.volume 30

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