DESIGN-FOR-TESTABILITY AND DIAGNOSIS METHODS TO TARGET UNMODELED DEFECTS IN INTEGRATED CIRCUITS AND MULTI-CHIP BOARDS

Abstract

<p>Very deep sub-micron process technologies are leading to increasing defect rates for integrated circuits (ICs) and multi-chip boards. To ensure the quality of test patterns and more effective defect screening, functional tests, delay tests, and n-detect tests are commonly used in industry for detecting unmodeled defects. However, the resulting test data volume and test application time are prohibitively high. Moreover, functional tests suffer from low defect coverage since they are mostly derived in practice from existing design-verification test sequences. Another challenge is that it is hard to find the root cause for board-level functional failures caused by various types of unmodeled defects. Therefore, there is a need for efficient testing, design-for-testability (DFT), and fault diagnosis methods to target these unmodeled defects.</p><p>To address the problem of high test data volume, a number of test ompression methods have been proposed in the literature based on Linear-Feedback-Shift-Register (LFSR) reseeding. A seed can be computed for each test cube by solving a system of linear equations based on the feedback polynomial of the LFSR. To improve the effectiveness of these seeds for unmodeled defects, this thesis shows how the recently proposed output-deviations metric can be used to select appropriate LFSR seeds. To further reduce the requirement for automatic test equipment (ATE) memory, the thesis describes a DFT technique for increasing the effectiveness of LFSR reseeding for unmodeled defects, which relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations.</p><p>Functional test sequences are often used in manufacturing testing to target defects that are not detected by structural test. In order to reduce the test application time caused by long functional test, which is needed to obtain high defect coverage, a deviation-based method to grade functional test sequences at register transfer (RT)-level is presented. The effectiveness of the proposed method is evaluated by the correlation between the RT-level deviations and gate-level fault coverage. It is also evaluated on the basis of coverage ramp-up data. Since functional test usually suffer from low defect coverage, there is a need to increase their effectiveness using DFT techniques. A DFT method has therefore been developed--it uses the register-transfer level (RTL) output-eviations metric to select observation points for an RTL design and a given functional test sequence.</p><p>A common scenario in industry is "No Trouble Found" (NTF), which means that each chip on the board passes the ATE test while it fails during board-level test. In such case, it is necessary to perform diagnosis at board-level to find the root cause. A promising approach to address this problem is to carry out fault diagnosis in two phases--suspect faulty components on the board or modules within components are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in ranked order. In this thesis, a new method based on dataflow analysis and Dempster-Shafer theory is presented for ranking faulty blocks in the first phase of diagnosis.</p><p>To find the root cause of NTF, an innovative functional test approach and DFT methods have been developed for the detection of board-level functional failures. These DFT and test methods allow us to reproduce and detect functional failures in a controlled deterministic environment, which can provide ATE tests to the supplier for early screening of defective parts.</p><p>In summary, this research is targeted at the testing, DFT, and diagnosis of unmodeled defects. The proposed techniques are expected to provide high-quality and compact test patterns, and effective DFT methods for various types of defects in integrated circuits. It is also expected to provide accurate diagnosis to find the root cause of defects in multi-chip boards.</p>