Abstract:
Three-dimensional (3D) integration is an attractive
technology platform for next-generation ICs. Despite the benefits
offered by 3D integration, test cost remains a major concern,
and analysis and tools are needed to understand test flows and
minimize test cost. We propose a generic cost model to account
for various test costs involved in 3D integration and present a
heuristic solution to minimize the overall manufacturing cost. In
contrast to prior work, which is based on explicit enumeration of
test flows, we adopt a formal optimization approach, which allows
us to select an effective test flow by systematically exploring an
exponentially large number of candidate test flows. Experimental
results highlight the effectiveness of the proposed heuristic
approach, which is compared to an exact approach for small test
cases (three dies) and to a random-selection baseline methods for
large test cases (up to 10 dies).
