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dc.contributor.author Agrawal, Mukesh
dc.contributor.author Chakrabarty, Krishnendu
dc.contributor.author Eklow, Bill
dc.date.accessioned 2012-10-26T12:52:19Z
dc.date.available 2012-10-26T12:52:19Z
dc.date.issued 2012-10-26
dc.identifier.uri http://hdl.handle.net/10161/5940
dc.description.abstract Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3D integration and present a heuristic solution to minimize the overall manufacturing cost. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed heuristic approach, which is compared to an exact approach for small test cases (three dies) and to a random-selection baseline methods for large test cases (up to 10 dies). en_US
dc.language.iso en_US en_US
dc.relation.ispartofseries ECE;2012-4
dc.subject 3D integration, cost modeling, heuristic optimization en_US
dc.title Test-Cost Optimization and Test-Flow Selection for 3D-Stacked ICs en_US
dc.type Technical Report en_US

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