Browsing by Author "Agrawal, M"

Filter results by typing the first few letters
Now showing 1 - 3 of 3
  • Thumbnail Image
    ItemOpen Access
    Test-Cost Modeling and Optimal Test-Flow Selection of 3D-Stacked ICs
    (2015-03-02) Agrawal, M; Chakrabarty, K
    Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost.We propose a generic cost model to account for various test costs involved in 3D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A*—a best-first search technique—to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.
  • Thumbnail Image
    ItemOpen Access
    Test-Cost Optimization and Test-Flow Selection for 3D-Stacked ICs
    (2012-10-26) Agrawal, M; Chakrabarty, K
    Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost. We propose a generic cost model to account for various test costs involved in 3D integration and present a heuristic solution to minimize the overall manufacturing cost. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed heuristic approach, which is compared to an exact approach for small test cases (three dies) and to a random-selection baseline methods for large test cases (up to 10 dies).
  • Thumbnail Image
    ItemOpen Access
    Test-Delivery Optimization in Manycore SOCs
    (2013-03-18) Agrawal, M; Richter, M; Chakrabarty, K
    We present two test-data delivery optimization algorithms for system on-chip (SOC) designs with hundreds of cores, where a network-on-chip (NOC) is used as the interconnection fabric. We first present an e ective algorithm based on a subsetsum formulation to solve the test-delivery problem in NOCs with arbitrary topology that use dedicated routing. We further propose an algorithm for the important class of NOCs with grid topology and XY routing. The proposed algorithm is the first to co-optimize the number of access points, access-point locations, pin distribution to access points, and assignment of cores to access points for optimal test resource utilization of such NOCs. Testtime minimization is modeled as an NOC partitioning problem and solved with dynamic programming in polynomial time. Both the proposed methods yield high-quality results and are scalable to large SOCs with many cores. We present results on synthetic grid topology NOC-based SOCs constructed using cores from the ITC’02 benchmark, and demonstrate the scalability of our approach for two SOCs of the future, one with nearly 1,000 cores and the other with 1,600 cores. Test scheduling under power constraints is also incorporated in the optimization framework.