Browsing by Author "Brooke, Martin A"
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Item Open Access A diffuse reflectance spectral imaging system for tumor margin assessment using custom annular photodiode arrays.(Biomedical optics express, 2012-12) Dhar, Sulochana; Lo, Justin Y; Palmer, Gregory M; Brooke, Martin A; Nichols, Brandon S; Yu, Bing; Ramanujam, Nirmala; Jokerst, Nan MDiffuse reflectance spectroscopy (DRS) is a well-established method to quantitatively distinguish between benign and cancerous tissue for tumor margin assessment. Current multipixel DRS margin assessment tools are bulky fiber-based probes that have limited scalability. Reported herein is a new approach to multipixel DRS probe design, which utilizes direct detection of the DRS signal by using optimized custom photodetectors in direct contact with the tissue. This first fiberless DRS imaging system for tumor margin assessment consists of a 4 × 4 array of annular silicon photodetectors and a constrained free-space light delivery tube optimized to deliver light across a 256 mm(2) imaging area. This system has 4.5 mm spatial resolution. The signal-to-noise ratio measured for normal and malignant breast tissue-mimicking phantoms was 35 dB to 45 dB for λ = 470 nm to 600 nm.Item Open Access A Serial Bitstream Processor for Smart Sensor Systems(2010) Cai, XinA full custom integrated circuit design of a serial bitstream processor is proposed for remote smart sensor systems. This dissertation describes details of the architectural exploration, circuit implementation, algorithm simulation, and testing results. The design is fabricated and demonstrated to be a successful working processor for basic algorithm functions. In addition, the energy performance of the processor, in terms of energy per operation, is evaluated. Compared to the multi-bit sensor processor, the proposed sensor processor provides improved energy efficiency for serial sensor data processing tasks, and also features low transistor count and area reduction advantages.
Operating in long-term, low data rate sensing environments, the serial bitstream processor developed is targeted at low-cost smart sensor systems with serial I/O communication through wireless links. This processor is an attractive option because of its low transistor count, easy on-chip integration, and programming flexibility for low data duty cycle smart sensor systems, where longer battery life, long-term monitoring and sensor reliability are critical.
The processor can be programmed for sensor processing algorithms such as delta sigma processor, calibration, and self-test algorithms. It also can be modified to utilize Coordinate Rotation Digital Computer (CORDIC) algorithms. The applications of the proposed sensor processor include wearable or portable biomedical sensors for health care monitoring or autonomous environmental sensors.
Item Open Access Efficient Test Methods for RF Transceivers(2010) Erdogan, Erdem SerkanAdvancements of the semiconductor technology opened a new era in
wireless communications which led manufacturers to produce faster,
more functional devices in much smaller sizes. However, testing
these devices of today's technology became much harder and expensive
due to the complexity of the devices and the high operating speeds.
Moreover, testing these devices becomes more important since decreasing
feature sizes increase the probability of parametric and catastrophic
faults because of the severe effects of process variations. Manufacturers
have to increase their test budgets to address quality and reliability
concerns. In the radio frequency (RF) domain, overall test cost are higher
due to equipment costs, test development and test time costs. Advanced
circuit integration, which integrates various analog and digital circuit
blocks into single device, increases test costs further because of the
additional tests requiring new test setups with extra test equipments.
Today's RF transceiver circuits contain many analog and digital circuit
blocks, such as synthesizers, data converters and the analog RF front-end
leading to a mixed signal device. Verification of the specifications and
functionality of each circuit block and the overall transceiver require
RF instrumentation and lengthy test routines. In this dissertation, we
propose efficient component and system level test methods for RF
transceivers which are low cost alternatives to traditional tests.
In the first component level test, we focus on in-band phase noise of the
phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at
measuring the timing jitter that may require precise reference clocks and/or
additional computation of measured specs. We propose a built in test (BiT)
circuit to perform a go/no-go test for in-band PLL phase noise. The proposed
circuit measures the band-limited noise power at the input of the voltage
controlled oscillator (VCO). This noise power is translated as the high
frequency in-band phase noise at the output of the PLL. Our circuit contains
a self calibration sequence based on a simple sinusoidal input signal to make
it robust with respect to process variations.
The second component level test is a built in self test (BiST) scheme
proposed for analog to digital converters (ADC) based on a linear ramp
generator and efficient output analysis. The proposed analysis method is
an alternative to histogram based analysis techniques to provide test time
improvements, especially when the resources are scarce. In addition to the
measurement of differential nonlinearity (DNL) and integral nonlinearity
(INL), non-monotonic behavior of the ADC can also be detected with the
proposed technique. The proposed ramp generator has a high linearity
capable of testing 13-bit ADCs.
In the proposed system level test methods, we utilize the loop-back
configuration to eliminate the need for an RF instrument. The first loop-back
test method, which is proposed for wafer level test of direct conversion
transceivers, targets catastrophic and large parametric faults. The use of
intermediate frequencies (IF) generates a frequency offset between the transmit
and receive paths and prevents a direct loop-back connection. We overcome this
problem by expanding the signal bandwidth through saturating the receive path
composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the
receiver path is determined, complete transceiver can be tested for catastrophic
signal path faults by observing the output signal. A frequency spectrum
envelope signature technique is proposed to detect large parametric faults.
The impact of impairments, such as transmitter receiver in-phase/quadrature
(I/Q) gain and phase mismatches on the performance have become severe due to
high operational speeds and continuous technology scaling. In the second system
level loop-back test method, we present BiST solutions for quadrature modulation
transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian
minimum shift keying (GMSK) baseband modulation schemes. The BiST methods
use only transmitter and receiver baseband signals for test analysis. The
mapping between transmitter input signals and receiver output signals are
used to extract impairment and nonlinearity parameters separately with the
help of signal processing methods and detailed nonlinear system modeling.
The last system level test proposed in this dissertation combines the benefits
of loop-back and multi-site test approaches. In this test method, we present
a 2x-site test solution for RF transceivers. We perform all operations on
communication standard-compliant signal packets, thereby putting the device
under the normal operating conditions. The transmitter on one device under
test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX
path. Parameters of the two devices are decoupled from one another by carefully
modeling the system into a known format and using signal processing techniques.
Item Open Access Modeling, Fabrication, and Test of a CMOS Integrated Circuit Platform for Electrophoretic Control of On-Chip Heterogeneous Fluids: toward Particle Separation on a Custom CMOS Chip(2009) Wake, Heather AnneElectrophoresis is the migration of charged particles in a heterogeneous fluid under the influence of an electric field. This project is work toward an electrophoretic separation system on a custom CMOS chip. Modeling, fabrication, and testing of an AMI ABN 1.5 um CMOS chip for this application is discussed. The unique approach is to build the entire system using conventional CMOS integrated circuit technology, such that the separation area is fabricated on the chip with integrated control and detection circuitry. To achieve the desired functionality, a novel configuration of an electrophoresis system is implemented. In this system, instead of using only one electrode at each end of the separation area, a multitude of electrodes beneath the entire separation area are utilized, enabling better control of high electric fields using very small voltages over small areas. Electronic circuits control the position and strength of the electric field to drive the separations and to simultaneously detect the location and concentration of samples within the separation area. Ultimately, the project was successful at showing that implementing an electrophoresis system on standard CMOS is possible.
Item Open Access Wide-Dynamic-Range Continuous-Time Delta-Sigma A/D Converter for Low-Power Energy Scavenging Applications(2011) Aleksanyan, ArnakMany medical, environmental, and industrial control applications rely on wide-dynamic-range sensors and A/D converter systems. For most photo-detector-based applications, the input-current is integrated onto a capacitor, either with a variable time, or a variable capacitor value, followed by a sample-and-hold and a voltage A/D converter. The penalty for achieving wide-dynamic-range with the above approach is power and circuit complexity.
We propose to use the unique properties of current-input continuous-time Delta-Sigma A/D converters to combine the photo-detector current-integration with simultaneous wide-dynamic-range A/D conversion, using programmable reference currents and programmable clock frequencies.
A programmable current-input wide-dynamic-range Delta-Sigma A/D converter is designed and fabricated using MOSIS AMI 1.5 um 5 V CMOS process. The programmable A/D converter test results exhibit a consistent 12-bit resolution over the programmability range of the reference-currents, from 17.2 nA to 4.4 uA. The supply-current varies from 60 uA to 240 uA, whereas the A/D converter sample-rates increase from 4 Samples/s to 1 kSamples/s, achieving an overall system-dynamic-range of 20-bits.
An RF-powered version is designed and fabricated using MOSIS ON 0.5 um 3 V CMOS process. It is designed to work at 128 Samples/s to 11.25 kSamples/s sample-rates, achieving 12-bit resolution with only 128 oversampling ratio. The A/D converter supply-current is designed to range from 10 uA to 70 uA to allow its integration with an RF-power source. The RF-powered version of the programmable Delta-Sigma A/D converter includes an on-chip voltage regulator that generates a stable 3 V DC-voltage, and consumes only 15 uA current.