Browsing by Author "Kavousianos, X"
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Item Open Access Generation of compact stuck-at test sets targeting unmodeled defects(IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011-05-01) Kavousianos, X; Chakrabarty, KThis letter presents a new method to generate compact stuck-at test sets that offer high defect coverage. The proposed method first selects the most effective patterns from a large $N$-detect repository, by using a new output deviation-based metric. Then it embeds complete coverage of stuck-at faults within these patterns, and uses the proposed metric to further improve their defect coverage. Results show that the proposed method outperforms a recently proposed competing approach in terms of unmodeled defect coverage. In many cases, higher defect coverage is obtained even than much larger $N$-detect test sets for several values of $N$. Finally, results provide the insight that, instead of using $N$- detect testing with as large $N$ as possible, it is more efficient to combine the output deviations metric with multi-detect testing to get high-quality, compact test sets. © 2006 IEEE.Item Open Access Time-division multiplexing for testing SoCs with DVS and multiple voltage islands(Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012, 2012-08-13) Kavousianos, X; Chakrabarty, K; Jain, A; Parekhji, RDynamic voltage scaling (DVS) has been widely adopted in multicore SoCs for reducing dynamic power consumption. Despite its benefits, the use of DVS increases test time because high product quality can only be ensured by testing every core at multiple supported voltage settings; hence the repetitive application of the same or different tests at multiple voltage settings becomes necessary. In addition, testing at lower supply voltage settings increases considerably the length of each test because lower scan frequencies must be used for shifting test data using scan chains. Standard scheduling techniques fail to reduce the test time for DVS-based SoCs since they do not model testing at multiple voltage settings. In addition, they do not consider the practical aspects of tester overhead and the dependencies between core voltage settings due to the use of voltage islands. To alleviate the detrimental impact of DVS on test application time, we propose a time-division multiplexing (TDM) method and an integer linear programming-based test scheduling technique, which exploit high automatic test equipment (ATE) frequencies even when low shift frequencies must be used at low voltage settings. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling method. © 2012 IEEE.