Browsing by Author "Lebeck, AR"

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    Architectural implications of nanoscale-integrated sensing and computing
    (IEEE Micro, 2010-01-01) Pistol, C; Chongchitmate, W; Dwyer, C; Lebeck, AR
    The authors explore nanoscale sensor processor (nSP) architectures. Their design includes a simple accumulator-based instruction-set architecture, sensors, limited memory, and instruction-fused sensing. Using nSP technology based on optical resonance energy transfer logic helps them decrease the design's size; their smallest design is about the size of the largest-known virus. © 2006 IEEE.
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    Modeling and simulation of a nanoscale optical computing system
    (Journal of Parallel and Distributed Computing, 2014-01-01) Pang, J; Lebeck, AR; Dwyer, C
    Optical nanoscale computing is one promising alternative to the CMOS process. In this paper we explore the application of Resonance Energy Transfer (RET) logic to common digital circuits. We propose an Optical Logic Element (OLE) as a basic unit from which larger systems can be built. An OLE is a layered structure that works similar to a lookup table but instead uses wavelength division multiplexing for its inputs and output. Waveguides provide a convenient mechanism to connect multiple OLEs into large circuits. We build a SPICE model from first principles for each component to estimate the timing and power behavior of the OLE system. We analyze various logic circuits and the simulation results show that the components are theoretically correct and that the models faithfully reproduce the fundamental phenomena; the power-delay product of OLE systems is at least 2.5× less than the 14 nm CMOS technology with 100× better density. © 2013 Elsevier Inc. All rights reserved.
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    More is Less, Less is More: Molecular-Scale Photonic NoC Power Topologies
    (ACM SIGPLAN NOTICES, 2015-04) Pang, J; Dwyer, C; Lebeck, AR
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    Nanoscale Resonance Energy Transfer-Based Devices for Probabilistic Computing
    (IEEE Micro, 2015-09-01) Lebeck, AR; Dwyer, CL; Wang, S
    © 1981-2012 IEEE.Despite the theoretical advances in probabilistic computing, a fundamental mismatch persists between the deterministic hardware that traditional computers use and the stochastic nature of probabilistic algorithms. In this article, the authors propose Resonance Energy Transfer (RET) between chromophores as an enabling technology for probabilistic computing functional units. As a natural continuous-time Markov chain, RET networks can physically implement efficient samplers with arbitrary probability distributions and have great potential for accelerating probabilistic algorithms.
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    Rhythm: Harnessing data parallel hardware for server workloads
    (International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS, 2014-03-14) Agrawal, SR; Pistol, V; Pang, J; Tran, J; Tarjan, D; Lebeck, AR
    Trends in increasing web traffic demand an increase in server throughput while preserving energy efficiency and total cost of ownership. Present work in optimizing data center efficiency primarily focuses on the data center as a whole, using off-the-shelf hardware for individual servers. Server capacity is typically increased by adding more machines, which is cheap, though inefficient in the long run in terms of energy and area. Our work builds on the observation that server workload execution patterns are not completely unique across multiple requests. We present a framework - called Rhythm - for high throughput servers that can exploit similarity across requests to improve server performance and power/energy efficiency by launching data parallel executions for request cohorts. An implementation of the SPECWeb Banking workload using Rhythm on NVIDIA GPUs provides a basis for evaluating both software and hardware for future cohort-based servers. Our evaluation of Rhythm on future server platforms shows that it achieves 4× the throughput (reqs/sec) of a core i7 at efficiencies (reqs/Joule) comparable to a dual core ARM Cortex A9. A Rhythm implementation that generates transposed responses achieves 8× the i7 throughput while processing 2.5× more requests/Joule compared to the A9. Copyright © 2014 ACM.
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    Unified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all
    (Proceedings - International Symposium on High-Performance Computer Architecture, 2010-05-27) Romanescu, BF; Lebeck, AR; Sorin, DJ; Bracy, A
    We propose UNITD, a unified hardware coherence framework that integrates translation coherence into the existing cache coherence protocol. In UNITD coherence protocols, the TLBs participate in the cache coherence protocol just like the instruction and data caches, without requiring any changes to the existing coherence protocol. UNITD eliminates the need for the software TLB shootdown routine, a procedure known to be performance costly and non-scalable. We evaluate snooping and directory UNITD coherence protocols on multicore processors with 2-16 cores, and we demonstrate that UNITD reduces the performance penalty associated with TLB coherence to almost zero. ©2009 IEEE.