Browsing by Subject "Testing"
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Item Open Access How Testing Serves African Americans in Epidemics, Past and Present: Applying Lessons from Tuberculosis to COVID-19 in the United States(2021-02-12) Chen, YuexuanRather than lacking the resources, knowledge or empirical evidence to successfully address testing inequities in the African American community, the U.S. lacks the imagination and commitment to directly confronting structural inequities that lead to failures in testing strategies for tuberculosis (TB) and COVID-19. Historical case studies showing successes and failures of TB testing campaigns in the African American community hold lessons that we can incorporate into our current and future public health measures in infectious disease outbreaks. This way—whether it’s an ancient bacteria like TB or a novel virus like COVID-19—we can work toward ensuring that insufficient trust in and access to high-quality, reliable tests will not be obstacles to improving equity in health outcomes. Further research on the nuances of how infectious disease testing has served other minority groups in the U.S. is recommended.Item Open Access Increasing access and uptake of SARS-CoV-2 at-home tests using a community-engaged approach.(Preventive medicine reports, 2022-10) D'Agostino, Emily M; Corbie, Giselle; Kibbe, Warren A; Hornik, Christoph P; Richmond, Al; Dunston, Angella; Damman, Allyn; Wruck, Lisa; Alvarado, Manuel; Cohen-Wolkowiez, MichaelInequalities around COVID-19 testing and vaccination persist in the U.S. health system. We investigated whether a community-engaged approach could be used to distribute free, at-home, rapid SARS-CoV-2 tests to underserved populations. Between November 18-December 31, 2021, 400,000 tests were successfully distributed via 67 community partners and a mobile unit to a majority Hispanic/Latino/Spanish population in Merced County, California. Testing before gathering (59 %) was the most common testing reason. Asians versus Whites were more likely to test for COVID-19 if they had close contact with someone who may have been positive (odds ratio [OR] = 3.4, 95 % confidence interval [CI] = 1.7-6.7). Minors versus adults were more likely to test if they had close contact with someone who was confirmed positive (OR = 1.7, 95 % CI = 1.0-3.0), whereas Asian (OR = 4.1, 95 % CI = 1.2-13.7) and Hispanic/Latino/Spanish (OR = 2.5, 95 % CI = 1.0-6.6) versus White individuals were more likely to test if they had a positive household member. Asians versus Whites were more likely to receive a positive test result. Minors were less likely than adults to have been vaccinated (OR = 0.2, 95 % CI = 0.1-0.3). Among unvaccinated individuals, those who completed the survey in English versus Spanish indicated they were more likely to get vaccinated in the future (OR = 8.2, 95 % CI = 1.5-44.4). Asians versus Whites were less likely to prefer accessing oral COVID medications from a pharmacy/drug store only compared with a doctor's office or community setting (OR = 0.3, 95 % CI = 0.2-0.6). Study findings reinforce the need for replicable and scalable community-engaged strategies for reducing COVID-19 disparities by increasing SARS-CoV-2 test and vaccine access and uptake.Item Open Access Optimization, Testing and Design-for-Testability of Flow-Based Microfluidic Biochips(2015-01-01) Hu, KaiFlow-based microfluidic biochips constitute an emerging technology for the automation of biochemical procedures. Recent advances in fabrication techniques have enabled the development of these devices. Increasing integration levels provide biochips with tremendous potential; a large number of bioassays, i.e., protocols for biochemistry, can be processed independently, simultaneously, and automatically on a coin-sized microfluidic platform. However, the increases in integration level introduce new challenges in the design optimization and the testing of these devices, which impede their further adoption and deployment.
This thesis is focused on enhancing the automated design and use of flow-based microfluidic biochips and on developing a set of solutions to facilitate the full exploitation of design complexities that are possible with current fabrication techniques. Four key research challenges are addressed in the thesis; these include design automation, wash optimization, testing, and defect diagnosis.
Despite the increase in the number of on-chip valves, designers are still using full-custom methodologies involving many manual steps to implement these chips. Since these chips can easily have thousands of valves, manual design procedure can be time-consuming and error-prone, and it can result in inefficient designs. This thesis presents the first problem formulation for automated control-layer design in flow-based microfluidic biochips and describes a systematic approach for solving this problem. Our goal is to find an efficient routing solution for control-layer design with a minimum number of control pins.
The problem of contamination removal in flow-based microfluidic biochips must also be addressed. Applications in biochemistry require high precision to avoid erroneous assay outcomes, and they are vulnerable to contamination between two fluidic flows with different biochemistries. This thesis proposes the first approach for automated wash optimization for contamination removal in flow-based microfluidic biochips. The proposed approach ensures effective cleaning and targets the generation of wash pathways to clean all contaminated microchannels with minimum execution time under physical constraints.
Another practical problem addressed in this thesis is the lack of test techniques for screening defective biochips before they are used for biochemical analysis. This thesis presents an efficient approach for automated testing of flow-based microfluidic biochips. The test technique is based on a behavioral abstraction of physical defects in microchannels and valves. The flow paths and flow control in the microfluidic device are modeled as a logic circuit composed of Boolean gates, which allows test generation to be carried out using standard automatic test-pattern generation tools. Based on the analysis of untestable faults in the logic-circuit model, we present a design-for-testability technique that can achieve 100\% fault coverage.
Finally, this thesis presents a technique for the automated diagnosis of leakage and blockage defects. The proposed method targets the identification of defect types and their locations based on test outcomes. It reduces the number of possible defect sites significantly while identifying their exact locations.
In summary, this thesis has led to a set of optimization and testing methods for flow-based microfluidic biochips. The results of this research are expected to not only shorten the product development cycle, but also accelerate the adoption and further development of this emerging technology by facilitating the full exploitation of design complexities that are possible with current fabrication techniques.
Item Open Access Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits(2019) Koneru, AbhishekThree-dimensional (3D) integration is a promising way to sustain Moore's Law beyond device- and interconnect-scaling limits. 3D technologies enable the integration of heterogeneous fabrication processes, and provide high-speed interconnects, high device-integration density, and low power consumption. Today's 3D technologies can broadly be classified into two categories based on the integration process: (i) 3D die/wafer stacking, in which separately manufactured dies/wafers are integrated onto the same package, and (ii) monolithic 3D (M3D) integration, in which transistor layers are processed sequentially on the same wafer. Through-silicon-vias (TSVs) are used to connect dies to each other in a 3D stacked integrated circuit (IC). In contrast, M3D ICs use inter-layer-vias (ILVs) of much smaller dimensions to connect a metal line in one transistor layer to a metal line in another transistor layer.
TSV-based 3D stacked ICs can be manufactured without requiring substantial changes to the existing fabrication flow. Considerable research efforts have therefore been directed towards the development of TSV-based 3D stacking technology, and products based on this technology have been successfully introduced into the marketplace, e.g., the AMD Fiji chip. However, the keep-out-zone (KOZ) required for TSVs and limitations on the die alignment precision impose limits on the device integration density that can be achieved using TSV-based 3D stacking. A minimum KOZ of 3 um is required for ICs fabricated at the 20 nm technology node, and the die alignment precision is currently limited to 0.5 um.
The above limitations on integration density can be overcome by adopting M3D integration. High-density integration in M3D is enabled by the alignment precision of ILVs, which is determined by the lithography stepper accuracy and has been reported to be 10 nm for the 22 nm technology node. In addition, the size and pitch of an ILV are typically one to two orders of magnitude smaller than those of a TSV. Therefore, M3D integration can result in reduced area and higher performance when compared to 3D die stacking.
Due to the above benefits of M3D integration, there is a growing interest in industry towards the adoption of this technology. However, test challenges for M3D integration have remained largely unexplored. This thesis is focussed on four key test challenges for M3D integration: (i) performance variations due to high-density integration, (ii) defect analysis and modeling, (iii) defect isolation and yield enhancement, and (iv) yield loss due to voltage droop. For each test challenge, we motivate the need to study its impact on an M3D IC, analyze the effectiveness of existing test solutions, and develop new solutions.
This dissertation first addresses challenges (i) and (ii). We quantify the impact of electrostatic coupling and wafer-bonding defects on the threshold voltage of a top-layer transistor in an M3D IC. In addition, we show that wafer-bonding defects can lead to a change in the resistance of ILVs, and in some cases, lead to an open in an ILV or a short between two ILVs. We also study the impact of these defects on path delays and on the effectiveness of delay-test patterns for large benchmarks. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its inter-layer dielectric is less than 100 nm.
Next, this dissertation presents a new DfT solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed DfT solution and compare it with that for a potential DfT solution based on the proposed IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of ILV density, ILV yield, and defect density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs.
This dissertation then presents an ILV BIST solution for M3D ICs to address isolation of ILV defects and yield enhancement. In the proposed ILV BIST solution, interface-register cells in a test layer are stitched into a TRC using their functional outputs and the ILVs. We show that the proposed solution detects all hard opens and shorts in the ILVs. We validate the detection of all hard opens and shorts using HSpice simulations. We also implement an artificial neural network-based diagnosis framework to estimate the size of ILV defect and show that the prediction accuracy of the proposed framework is extremely high.
Finally, this dissertation describes an optimization approach for reliable power delivery in M3D ICs to address challenge (iv). We analyze the voltage droop during testing and compare it with that observed during functional operation. We also quantify the impact of voltage droop during testing on yield loss. Our results show that the proposed power delivery optimization approach significantly reduces the worst-case voltage droop and yield loss due to voltage droop compared to a baseline.
In summary, the dissertation targets important design and optimization problems related to testing of M3D ICs. This research has led to theoretical insights, significant academic and industrial collaborations, simulations results using advanced process design kits, and a set of test and DfT solutions.