ALERT: This system is being upgraded on Tuesday December 12. It will not be available for use for several hours that day while the upgrade is in progress. Deposits to DukeSpace will be disabled on Monday December 11, so no new items are to be added to the repository while the upgrade is in progress. Everything should be back to normal by the end of day, December 12.

Browsing by Subject "3D chip testing"

Now showing items 1-1 of 1

    • Test-Cost Modeling and Optimal Test-Flow Selection of 3D-Stacked ICs 

      Agrawal, M; Chakrabarty, K (2015-03-02)
      Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand ...