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Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits

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Date
2010-03-29
Authors
Chakrabarty, Krishnendu
Tehranipoor, Mohammad
Yilmaz, Mahmut
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Abstract
Timing-related defects are a major cause for test escapes and field returns for very-deep-sub-micron (VDSM) integrated circuits (ICs). Small-delay variations induced by crosstalk, process variations, power-supply noise, and resistive opens and shorts can cause timing failures in a design, thereby leading to quality and reliability concerns. We present the industrial application and case study of a previously proposed test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). The technique is shown to have significantly lower computational complexity and test pattern count, without loss of test quality, compared to a commercial timing-aware automatic test pattern generation (ATPG) tool.
Type
Report
Subject
delay test
output deviations
Permalink
https://hdl.handle.net/10161/2137
Citation
Chakrabarty, Krishnendu; Tehranipoor, Mohammad; & Yilmaz, Mahmut (2010). Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits. Retrieved from https://hdl.handle.net/10161/2137.
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Chakrabarty

Krishnendu Chakrabarty

John Cocke Distinguished Professor of Electrical and Computer Engineering
Krishnendu Chakrabarty is the John Cocke Distinguished Professor of Electrical and Computer Engineering and Professor of Computer Science at Duke University.
This author no longer has a Scholars@Duke profile, so the information shown here reflects their Duke status at the time this item was deposited.

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