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Efficient Test Methods for RF Transceivers

dc.contributor.advisor Brooke, Martin A
dc.contributor.advisor Ozev, Sule Erdogan, Erdem Serkan 2010-05-10T19:57:29Z 2012-05-01T04:30:05Z 2010
dc.description.abstract <p>Advancements of the semiconductor technology opened a new era in</p> <p>wireless communications which led manufacturers to produce faster,</p> <p>more functional devices in much smaller sizes. However, testing</p> <p>these devices of today's technology became much harder and expensive</p> <p>due to the complexity of the devices and the high operating speeds.</p> <p>Moreover, testing these devices becomes more important since decreasing</p> <p>feature sizes increase the probability of parametric and catastrophic</p> <p>faults because of the severe effects of process variations. Manufacturers</p> <p>have to increase their test budgets to address quality and reliability</p> <p>concerns. In the radio frequency (RF) domain, overall test cost are higher</p> <p>due to equipment costs, test development and test time costs. Advanced</p> <p>circuit integration, which integrates various analog and digital circuit</p> <p>blocks into single device, increases test costs further because of the</p> <p>additional tests requiring new test setups with extra test equipments.</p> <p>Today's RF transceiver circuits contain many analog and digital circuit</p> <p>blocks, such as synthesizers, data converters and the analog RF front-end</p> <p>leading to a mixed signal device. Verification of the specifications and</p> <p>functionality of each circuit block and the overall transceiver require</p> <p>RF instrumentation and lengthy test routines. In this dissertation, we</p> <p>propose efficient component and system level test methods for RF</p> <p>transceivers which are low cost alternatives to traditional tests.</p> <p>In the first component level test, we focus on in-band phase noise of the</p> <p>phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at</p> <p>measuring the timing jitter that may require precise reference clocks and/or</p> <p>additional computation of measured specs. We propose a built in test (BiT)</p> <p>circuit to perform a go/no-go test for in-band PLL phase noise. The proposed</p> <p>circuit measures the band-limited noise power at the input of the voltage</p> <p>controlled oscillator (VCO). This noise power is translated as the high</p> <p>frequency in-band phase noise at the output of the PLL. Our circuit contains</p> <p>a self calibration sequence based on a simple sinusoidal input signal to make</p> <p>it robust with respect to process variations.</p> <p>The second component level test is a built in self test (BiST) scheme</p> <p>proposed for analog to digital converters (ADC) based on a linear ramp</p> <p>generator and efficient output analysis. The proposed analysis method is</p> <p>an alternative to histogram based analysis techniques to provide test time</p> <p>improvements, especially when the resources are scarce. In addition to the</p> <p>measurement of differential nonlinearity (DNL) and integral nonlinearity</p> <p>(INL), non-monotonic behavior of the ADC can also be detected with the</p> <p>proposed technique. The proposed ramp generator has a high linearity</p> <p>capable of testing 13-bit ADCs.</p> <p>In the proposed system level test methods, we utilize the loop-back</p> <p>configuration to eliminate the need for an RF instrument. The first loop-back</p> <p>test method, which is proposed for wafer level test of direct conversion</p> <p>transceivers, targets catastrophic and large parametric faults. The use of</p> <p>intermediate frequencies (IF) generates a frequency offset between the transmit</p> <p>and receive paths and prevents a direct loop-back connection. We overcome this</p> <p>problem by expanding the signal bandwidth through saturating the receive path</p> <p>composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the</p> <p>receiver path is determined, complete transceiver can be tested for catastrophic</p> <p>signal path faults by observing the output signal. A frequency spectrum</p> <p>envelope signature technique is proposed to detect large parametric faults.</p> <p>The impact of impairments, such as transmitter receiver in-phase/quadrature</p> <p>(I/Q) gain and phase mismatches on the performance have become severe due to</p> <p>high operational speeds and continuous technology scaling. In the second system</p> <p>level loop-back test method, we present BiST solutions for quadrature modulation</p> <p>transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian</p> <p>minimum shift keying (GMSK) baseband modulation schemes. The BiST methods</p> <p>use only transmitter and receiver baseband signals for test analysis. The</p> <p>mapping between transmitter input signals and receiver output signals are</p> <p>used to extract impairment and nonlinearity parameters separately with the</p> <p>help of signal processing methods and detailed nonlinear system modeling.</p> <p>The last system level test proposed in this dissertation combines the benefits </p> <p>of loop-back and multi-site test approaches. In this test method, we present </p> <p>a 2x-site test solution for RF transceivers. We perform all operations on </p> <p>communication standard-compliant signal packets, thereby putting the device </p> <p>under the normal operating conditions. The transmitter on one device under </p> <p>test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX </p> <p>path. Parameters of the two devices are decoupled from one another by carefully </p> <p>modeling the system into a known format and using signal processing techniques.</p>
dc.format.extent 8339500 bytes
dc.format.mimetype application/pdf
dc.language.iso en_US
dc.subject Engineering, Electronics and Electrical
dc.subject ADC
dc.subject Loop-back
dc.subject Multi-site
dc.subject RF Test
dc.subject Synthesizer
dc.subject Wafer Level
dc.title Efficient Test Methods for RF Transceivers
dc.type Dissertation
dc.department Electrical and Computer Engineering
duke.embargo.months 24

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