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Decoupled store completion/silent deterministic replay: Enabling scalable data memory for CPR/CFP processors
(Proceedings - International Symposium on Computer Architecture, 2009-11-30)
CPR/CFP (Checkpoint Processing and Recovery/Continual Flow Pipeline) support an adaptive instruction window that scales to tolerate last-level cache misses. CPR/CFP scale the register file by aggressively reclaiming the ...
Icfp: tolerating all-level cache misses in in-order processors
(Proceedings - International Symposium on High-Performance Computer Architecture, 2009-04-24)
Growing concerns about power have revived interest in in-order pipelines. In-order pipelines sacrifice single-thread performance. Specifically, they do not allow execution to flow freely around data cache misses. As a result, ...
CPROB: Checkpoint processing with opportunistic minimal recovery
(Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT, 2009-11-23)
CPR (Checkpoint Processing and Recovery) is a physical register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style register management. It does so by restricting ...