Now showing items 1-12 of 12

    • Decoupling Loads for Nano-Instruction Set Computers 

      Hilton, Andrew; Huang, Z; Lee, BC (Proceedings - 2016 43rd International Symposium on Computer Architecture, ISCA 2016, 2016-08-24)
      © 2016 IEEE.We propose an ISA extension that decouples the data access and register write operations in a load instruction. We describe system and hardware support for decoupled loads. Furthermore, we show how compilers ...
    • Error recovery in cyberphysical digital microfluidic biochips 

      Chakrabarty, Krishnendu; Ho, TY; Luo, Y (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013-01-07)
      Droplet-based digital microfluidics technology has now come of age, and software-controlled biochips for healthcare applications are starting to emerge. However, today's digital microfluidic biochips suffer from the drawback ...
    • Execution of Provably Secure Assays on MEDA Biochips to Thwart Attacks 

      Chakrabarty, Krishnendu; Liang, Tung-Che; Shayan, Mohammed; Karri, Ramesh (2018)
      Digital microfluidic biochips (DMFBs) have emerged as a promising platform for DNA sequencing, clinical chemistry, and point-of-care diagnostics. Recent research has shown that DMFBs are susceptible to various types of malicious ...
    • Fault Tolerance for RRAM-Based Matrix Operations 

      Chakrabarty, Krishnendu; Liu, Mengyun; Xia, Lixue; Wang, Yu
      An RRAM-based computing system (RCS) provides an energy efficient hardware implementation of vector-matrix multiplication for machine-learning hardware. However, it is vulnerable to faults due to the immature RRAM fabrication ...
    • Functional test-sequence grading at register-transfer level 

      Chakrabarty, Krishnendu; Fang, H; Jas, A; Patil, S; Tirumurti, C (IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012-01-01)
      We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the ...
    • Generation of compact stuck-at test sets targeting unmodeled defects 

      Chakrabarty, Krishnendu; Kavousianos, X (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011-05-01)
      This letter presents a new method to generate compact stuck-at test sets that offer high defect coverage. The proposed method first selects the most effective patterns from a large $N$-detect repository, by using a new output ...
    • Neurophysiology of Visual-Motor Learning during a Simulated Marksmanship Task in Immersive Virtual Reality 

      Appelbaum, Lawrence; Sommer, Marc; Kopper, Regis; Clements, JM; Zielinski, DJ; Rao, H; Kirsch, E; ... (9 authors) (25th IEEE Conference on Virtual Reality and 3D User Interfaces, VR 2018 - Proceedings, 2018-08-24)
      © 2018 IEEE. Immersive virtual reality (VR) systems offer flexible control of an interactive environment, along with precise position and orientation tracking of realistic movements. Immersive VR can also be used in conjunction ...
    • PoisonIvy: Safe speculation for secure memory 

      Hilton, Andrew; Lee, BC; Lehman, TS (Proceedings of the Annual International Symposium on Microarchitecture, MICRO, 2016-12-14)
      © 2016 IEEE.Encryption and integrity trees guard against physical attacks, but harm performance. Prior academic work has speculated around the latency of integrity verification, but has done so in an insecure manner. No ...
    • Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits 

      Chakrabarty, Krishnendu; Tehranipoor, Mohammad; Yilmaz, Mahmut (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010-05-01)
      Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply ...
    • Time-division multiplexing for testing SoCs with DVS and multiple voltage islands 

      Chakrabarty, Krishnendu; Jain, A; Kavousianos, X; Parekhji, R (Proceedings - 2012 17th IEEE European Test Symposium, ETS 2012, 2012-08-13)
      Dynamic voltage scaling (DVS) has been widely adopted in multicore SoCs for reducing dynamic power consumption. Despite its benefits, the use of DVS increases test time because high product quality can only be ensured by ...