| dc.contributor.author |
Pistol, C |
|
| dc.contributor.author |
Chongchitmate, W |
|
| dc.contributor.author |
Dwyer, C |
|
| dc.contributor.author |
Lebeck, AR |
|
| dc.date.accessioned |
2011-05-18T01:58:00Z |
|
| dc.date.issued |
2010-01-01 |
|
| dc.identifier.issn |
0272-1732 |
|
| dc.identifier.uri |
https://hdl.handle.net/10161/3766 |
|
| dc.description.abstract |
The authors explore nanoscale sensor processor (nSP) architectures. Their design includes
a simple accumulator-based instruction-set architecture, sensors, limited memory,
and instruction-fused sensing. Using nSP technology based on optical resonance energy
transfer logic helps them decrease the design's size; their smallest design is about
the size of the largest-known virus. © 2006 IEEE.
|
|
| dc.language.iso |
en_US |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
| dc.relation.ispartof |
IEEE Micro |
|
| dc.relation.isversionof |
10.1109/MM.2010.9 |
|
| dc.title |
Architectural implications of nanoscale-integrated sensing and computing |
|
| dc.type |
Journal article |
|
| duke.contributor.id |
Dwyer, C|0311124 |
|
| duke.contributor.id |
Lebeck, AR|0114435 |
|
| pubs.begin-page |
110 |
|
| pubs.end-page |
120 |
|
| pubs.issue |
1 |
|
| pubs.organisational-group |
Computer Science |
|
| pubs.organisational-group |
Duke |
|
| pubs.organisational-group |
Electrical and Computer Engineering |
|
| pubs.organisational-group |
Pratt School of Engineering |
|
| pubs.organisational-group |
Trinity College of Arts & Sciences |
|
| pubs.publication-status |
Published |
|
| pubs.volume |
30 |
|
| duke.contributor.orcid |
Lebeck, AR|0000-0003-1893-5464 |
|
