Modeling and Optimization of Emerging Technology-Based Artificial Intelligence Accelerators under Imperfections

Machine learning algorithms are emerging in a wide range of application domains, ranging from autonomous driving, real-time speech translation, and network anomaly detection to pandemic growth and trend prediction. In particular, deep learning, facilitated by highly parallelized processing in hardware accelerators, has received tremendous interest due to its effectiveness for solving complex tasks across different application domains. However, as Moore's law approaches its end, contemporary electronic deep-learning inferencing accelerators show diminishing energy efficiency and have been unable to cope with the performance demands from emerging deep learning applications. To mitigate these issues, there is a need for research efforts on emerging artificial intelligence (AI) accelerators that explore novel transistor technologies with high transconductance at the nanometer technology nodes and low-latency alternatives to metallic interconnects. In this dissertation, we focus on the modeling and optimization of two such technologies: (i) high-speed transistors built using carbon nanotubes (CNTs), and (ii) integrated photonic networks that parallelize matrix-vector multiplications.

CNTs are considered to be leading candidates for realizing beyond-silicon transistors. Owing to the ultra-thin body of CNTs and near-ballistic carrier transport, carbon nanotube field-effect transistors (CNFETs) demonstrate a high on-current/off-current ratio and low subthreshold swing. Integrated circuits (ICs) fabricated from CNFETs are projected to achieve an order of magnitude improvement in the energy-delay product compared to silicon MOSFETs. Despite these advances, several challenges related to yield and performance must be addressed before CNFET-based high-volume production can appear on industry roadmaps. While some of these challenges (e.g., shorts due to metallic CNTs and incorrect logic functionality due to misaligned CNTs) have been addressed, the impact of fabrication process variations and manufacturing defects has largely remained unexplored.

Silicon photonic networks have been known to outperform the existing communication infrastructure (i.e., metallic interconnect) in multi-processor systems-on-chip. In recent years, their application as compute platforms in AI accelerators has attracted considerable attention. Leveraging the inherent parallelism of optical computing, integrated photonic neural networks (IPNNs) can perform the otherwise time-intensive matrix multiplication in O(1) time. Given their competitive integration density, ultra-high energy efficiency, and good CMOS compatibility, IPNNs demonstrate order-of-magnitude higher performance and efficiency than their electronic counterparts. However, the performance of photonic components is highly sensitive to fabrication process variations, manufacturing defects, and crosstalk noise.

In this dissertation, we present the first comprehensive characterization of CNFETs and IPNNs under imperfections. In the case of CNFETs, we consider the impact of fabrication process variations in different device parameters and manufacturing defects that are commonly observed during fabrication. To characterize IPNNs, we consider uncertainties in phase angles and splitting ratios in their building blocks (i.e., Mach--Zehnder interferometers), non-uniform optical loss in the waveguides, and quantization errors due to low-precision encoding of tuned phase angles. Using detailed simulations, we show that these devices can deviate significantly from their nominal performance, even in mature fabrication processes. For example, we show that more than 90% CNFETs can fail due to a 5% change in the CNT diameter. Similarly, the inferencing accuracy of IPNNs can drop below 10% due to uncertainties in the phase angles and splitting ratios.

To ensure the adoption of accelerators based on CNFETs and IPNNs, techniques to test and mitigate the catastrophic impact of imperfections are necessary. As the nature of imperfection in CNFETs vary significantly from those in Si-MOSFETs, existing commercial test pattern generation tools are inefficient when they are applied to ICs with imperfect CNFETs. This thesis presents VADF, a novel CNFET variation-aware test pattern generation tool that significantly improves the efficiency of small delay defect testing under imperfections. Unetched CNTs in the active layer can lead to parasitic FETs that can cause resistive shorts. In addition, we propose ParaMitE, which is a low-cost optimization technique, to reduce the probability of para-FET occurrence and mitigate their impact on performance. The thesis also describes three optimization techniques to improve the power-efficiency and reliability of IPNNs under imperfections. OptimSVD leverages non-uniqueness of the singular value decomposition to minimize the phase angles in an IPNN while guaranteeing zero accuracy loss. We propose CHAMP and LTPrune, which, to the best of our knowledge, are the only photonic hardware-aware magnitude pruning techniques targeted towards IPNNs.

In summary, this dissertation tackles important problems related to the reliability and high-volume yield of next-generation AI accelerators. We show how the criticality of different imperfections can change based on their magnitude and also the location and parameters of the affected components. The methods presented in this dissertation, while targeted towards CNFETs and IPNNs, can be easily extended towards other emerging technologies leveraged for AI hardware. The insights derived from this work can help designers to develop post-silicon AI accelerators that, in addition to demonstrating superior nominal performance, are resilient to inevitable imperfections.