Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits

Loading...
Thumbnail Image

Date

2010-03-29

Authors

Chakrabarty, Krishnendu
Yilmaz, Mahmut

Journal Title

Journal ISSN

Volume Title

Repository Usage Stats

368
views
531
downloads

Abstract

Timing-related defects are a major cause for test escapes and field returns for very-deep-sub-micron (VDSM) integrated circuits (ICs). Small-delay variations induced by crosstalk, process variations, power-supply noise, and resistive opens and shorts can cause timing failures in a design, thereby leading to quality and reliability concerns. We present the industrial application and case study of a previously proposed test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). The technique is shown to have significantly lower computational complexity and test pattern count, without loss of test quality, compared to a commercial timing-aware automatic test pattern generation (ATPG) tool.

Department

Description

Provenance

Citation

Citation

Chakrabarty, Krishnendu, Mohammad Tehranipoor and Mahmut Yilmaz (2010). Adaptation and Evaluation of the Output-Deviations Metric to Target Small-Delay Defects in Industrial Circuits. Retrieved from https://hdl.handle.net/10161/2137.


Material is made available in this collection at the direction of authors according to their understanding of their rights in that material. You may download and use these materials in any manner not prohibited by copyright or other applicable law.