Functional test-sequence grading at register-transfer level

dc.contributor.author

Fang, H

dc.contributor.author

Chakrabarty, K

dc.contributor.author

Jas, A

dc.contributor.author

Patil, S

dc.contributor.author

Tirumurti, C

dc.date.accessioned

2011-07-12T20:47:58Z

dc.date.issued

2012-01-01

dc.description.abstract

We propose output deviations as a surrogate metric to grade functional test sequences at the register-transfer level without explicit fault simulation. Experimental results for the open-source Biquad filter core and the Scheduler module of the Illinois Verilog Model show that the deviations metric is computationally efficient and it correlates well with gate-level coverage for stuck-at, transition-delay and bridging faults. Results also show that functional test sequences reordered based on output deviations provide steeper gate-level fault coverage ramp-up compared to other ordering methods. © 2011 IEEE.

dc.identifier.issn

1063-8210

dc.identifier.uri

https://hdl.handle.net/10161/4641

dc.language.iso

en_US

dc.publisher

Institute of Electrical and Electronics Engineers (IEEE)

dc.relation.ispartof

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

dc.relation.ispartofseries

ECE;2011-01

dc.relation.isversionof

10.1109/TVLSI.2011.2163651

dc.title

Functional test-sequence grading at register-transfer level

dc.type

Journal article

pubs.begin-page

1890

pubs.end-page

1894

pubs.issue

10

pubs.organisational-group

Duke

pubs.organisational-group

Electrical and Computer Engineering

pubs.organisational-group

Pratt School of Engineering

pubs.publication-status

Published

pubs.volume

20

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