Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits

Loading...
Thumbnail Image

Date

2019

Journal Title

Journal ISSN

Volume Title

Repository Usage Stats

372
views
216
downloads

Abstract

Three-dimensional (3D) integration is a promising way to sustain Moore's Law beyond device- and interconnect-scaling limits. 3D technologies enable the integration of heterogeneous fabrication processes, and provide high-speed interconnects, high device-integration density, and low power consumption. Today's 3D technologies can broadly be classified into two categories based on the integration process: (i) 3D die/wafer stacking, in which separately manufactured dies/wafers are integrated onto the same package, and (ii) monolithic 3D (M3D) integration, in which transistor layers are processed sequentially on the same wafer. Through-silicon-vias (TSVs) are used to connect dies to each other in a 3D stacked integrated circuit (IC). In contrast, M3D ICs use inter-layer-vias (ILVs) of much smaller dimensions to connect a metal line in one transistor layer to a metal line in another transistor layer.

TSV-based 3D stacked ICs can be manufactured without requiring substantial changes to the existing fabrication flow. Considerable research efforts have therefore been directed towards the development of TSV-based 3D stacking technology, and products based on this technology have been successfully introduced into the marketplace, e.g., the AMD Fiji chip. However, the keep-out-zone (KOZ) required for TSVs and limitations on the die alignment precision impose limits on the device integration density that can be achieved using TSV-based 3D stacking. A minimum KOZ of 3 um is required for ICs fabricated at the 20 nm technology node, and the die alignment precision is currently limited to 0.5 um.

The above limitations on integration density can be overcome by adopting M3D integration. High-density integration in M3D is enabled by the alignment precision of ILVs, which is determined by the lithography stepper accuracy and has been reported to be 10 nm for the 22 nm technology node. In addition, the size and pitch of an ILV are typically one to two orders of magnitude smaller than those of a TSV. Therefore, M3D integration can result in reduced area and higher performance when compared to 3D die stacking.

Due to the above benefits of M3D integration, there is a growing interest in industry towards the adoption of this technology. However, test challenges for M3D integration have remained largely unexplored. This thesis is focussed on four key test challenges for M3D integration: (i) performance variations due to high-density integration, (ii) defect analysis and modeling, (iii) defect isolation and yield enhancement, and (iv) yield loss due to voltage droop. For each test challenge, we motivate the need to study its impact on an M3D IC, analyze the effectiveness of existing test solutions, and develop new solutions.

This dissertation first addresses challenges (i) and (ii). We quantify the impact of electrostatic coupling and wafer-bonding defects on the threshold voltage of a top-layer transistor in an M3D IC. In addition, we show that wafer-bonding defects can lead to a change in the resistance of ILVs, and in some cases, lead to an open in an ILV or a short between two ILVs. We also study the impact of these defects on path delays and on the effectiveness of delay-test patterns for large benchmarks. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its inter-layer dielectric is less than 100 nm.

Next, this dissertation presents a new DfT solution for M3D ICs based on dedicated test layers, which are inserted between functional layers. We evaluate the cost associated with the proposed DfT solution and compare it with that for a potential DfT solution based on the proposed IEEE Std. P1838. Our results show that the proposed DfT solution is more cost-efficient than the P1838-based DfT solution for a wide range of ILV density, ILV yield, and defect density. We also present a test scheduling and optimization technique for wafer-level testing of M3D ICs.

This dissertation then presents an ILV BIST solution for M3D ICs to address isolation of ILV defects and yield enhancement. In the proposed ILV BIST solution, interface-register cells in a test layer are stitched into a TRC using their functional outputs and the ILVs. We show that the proposed solution detects all hard opens and shorts in the ILVs. We validate the detection of all hard opens and shorts using HSpice simulations. We also implement an artificial neural network-based diagnosis framework to estimate the size of ILV defect and show that the prediction accuracy of the proposed framework is extremely high.

Finally, this dissertation describes an optimization approach for reliable power delivery in M3D ICs to address challenge (iv). We analyze the voltage droop during testing and compare it with that observed during functional operation. We also quantify the impact of voltage droop during testing on yield loss. Our results show that the proposed power delivery optimization approach significantly reduces the worst-case voltage droop and yield loss due to voltage droop compared to a baseline.

In summary, the dissertation targets important design and optimization problems related to testing of M3D ICs. This research has led to theoretical insights, significant academic and industrial collaborations, simulations results using advanced process design kits, and a set of test and DfT solutions.

Description

Provenance

Citation

Citation

Koneru, Abhishek (2019). Test and Design-for-Testability Solutions for Monolithic 3D Integrated Circuits. Dissertation, Duke University. Retrieved from https://hdl.handle.net/10161/18664.

Collections


Dukes student scholarship is made available to the public using a Creative Commons Attribution / Non-commercial / No derivative (CC-BY-NC-ND) license.