ICFP: Tolerating all-level cache misses in in-order processors
| dc.contributor.author | Hilton, A | |
| dc.contributor.author | Nagarakatte, S | |
| dc.contributor.author | Roth, A | |
| dc.date.accessioned | 2016-02-24T19:31:44Z | |
| dc.date.issued | 2010-01-01 | |
| dc.description.abstract | In-order continual flow pipeline (iCFP) is an in-order pipeline that allows execution to flow around data cache misses. When a cache miss occurs, iCFP executes and speculatively retires miss-independent instructions. It saves miss-dependent instructions in a slice buffer. When the miss returns, iCFP reexecutes the contents of the slice buffer and merges the results into working state. iCFP exploits existing support for multithreading and several novel components. © 2006 IEEE. | |
| dc.identifier.issn | 0272-1732 | |
| dc.identifier.uri | ||
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | IEEE Micro | |
| dc.relation.isversionof | 10.1109/MM.2010.20 | |
| dc.title | ICFP: Tolerating all-level cache misses in in-order processors | |
| dc.type | Journal article | |
| pubs.begin-page | 12 | |
| pubs.end-page | 19 | |
| pubs.issue | 1 | |
| pubs.organisational-group | Computer Science | |
| pubs.organisational-group | Duke | |
| pubs.organisational-group | Electrical and Computer Engineering | |
| pubs.organisational-group | Pratt School of Engineering | |
| pubs.organisational-group | Trinity College of Arts & Sciences | |
| pubs.publication-status | Published | |
| pubs.volume | 30 |