Testing and Fault Diagnosis Solutions for Monolithic 3D ICs

Abstract

As Moore’s Law hits physical limits, three-dimensional (3D) integration constitutes a promising technology to continue power, performance, and area (PPA) improvement. Among modern 3D integration technologies, monolithic 3D (M3D) has attracted a lot of attention because it offers better performance and lower power consumption compared to conventional 2D integrated circuits (ICs). However, the benefits of M3D integration are accompanied by new challenges. Recent research has shown that low-temperature manufacturing processes necessary for upper-tier fabrication can cause performance mismatch between device tiers. Interconnects between tiers, referred to as monolithic inter-tier vias (MIVs), are prone to defects due to the surface roughness of the inter-tier dielectric. These M3D-specific defects tend to be manifested in the form of delay faults that impact circuit timing. Moreover, power supply noise (PSN) is another concern for M3D ICs because of high power and current densities. Excessive voltage droop during delay testing may cause good chips to fail on the tester and lead to yield loss.Stacking memory on logic is one of the major applications of M3D integration. Combining M3D with the emerging resistive random-access memory (RRAM) has been shown to achieve extremely high memory density and improve power efficiency. However, both M3D and RRAM suffer from high defect rates due to immature manufacturing processes and process variations. Testing and fault diagnosis of memory-on-logic designs are therefore important to facilitate yield learning and shorten the time-to-market.Motivated by the aforementioned challenges, this dissertation focuses on developing effective testing and diagnosis solutions for M3D ICs. The dissertation first addresses the PSN-induced yield loss problem by test pattern reshaping. The dissertation presents an analysis framework to identify test patterns that are most likely to lead to yield loss. These patterns are subject to reshaping through two distinct algorithms based on integer linear programming (ILP) and simulated annealing (SA). Simulation results show that PSN-induced yield loss is eliminated with reshaped patterns. The dissertation also employs two design-for-test (DfT) methodologies, namely test point insertion (TPI) and scan segmentation, to minimize switching activities during testing. The TPI framework leverages reinforcement learning (RL) to determine the optimal types and locations of test points (TPs) for test power reduction; the RL-based scan segmentation framework effectively partitionsscan D-flip-flops (SDFFs) into segments and assigns enable signals to control these segments. Both frameworks have been demonstrated to ensure power-safe testing for M3D ICs without any adverse impact on test coverage.Next, the dissertation presents a fault localization framework using graph neural networks (GNNs) to identify tier-level fault locations during diagnosis. Leveraging circuit netlists and failure log files from the tester, the GNN-based framework efficiently localizes faults to device tiers, offering rapid feedback to the foundry and enhancing the quality of diagnosis reports. Moreover, this research develops a diagnosis procedure to identify the fault origin when an M3D-integrated RRAM device fails the manufacturing test. The dissertation presents a detailed characterization of RRAM faulty behaviors in the presence of concurrent process variations and manufacturing defects. Based on RRAM characteristics, a diagnosis sequence is developed by identifying appropriate reference resistance and applied voltages to efficiently distinguish fault origins. The dissertation also introduces a test sequence to detect faults due to PSN noise and quantify the magnitude of noise and defects within M3D-integrated multi-level cell (MLC) arrays. Simulation results have demonstrated the efficacy of the proposed test and diagnosis sequences on memory-on-logic stacking M3D devices.In summary, this dissertation addresses critical issues in the testing and diagnosis of M3D ICs. The outcomes of the dissertation provide theoretical insights and effective solutions for ensuring power-safe testing and facilitating yield learning. It is expected that the evolving M3D technology will derive significant benefits from these solutions as it progresses towards commercial viability.