Design and Testing of a Low-Noise, Low-Power, Scalable, Actively-Multiplexed Neural Interface

Abstract

Brain computer interfaces (BCIs) provide clinical benefits including partial restoration of lost motor control, vision, speech, and hearing. Neural interfaces are critical components of brain-computer interfaces (BCIs), bridging the gap between the brain and electronics. A major challenge in their design is balancing spatial coverage and resolution, as the number of recording channels is limited by connector sizes and backend electronics. Embedding active electronics at the electrode site to enable time-division multiplexing (TDM) increases channel count without adding output wires. TDM, however, introduces noise aliasing and fabrication-dependent transistor noise due to the limitations of university cleanrooms, which are not optimized for low-noise transistor fabrication. In contrast, industrial CMOS foundries are specifically designed for low-noise transistor fabrication at small feature sizes but utilize thick wafer substrates, creating challenges for their adaptation to flexible neural interfaces. Transfer printing offers a viable solution by enabling the transfer of active electronics onto flexible substrates, facilitating the large-scale integration of amplifiers and multiplexers necessary for functional low noise neural interfaces. In this dissertation, I developed a scalable, flexible, low-noise, low-power, and actively multiplexed neural interface by combining commercial integrated circuit design with transfer printing through a collaboration with Prof. Hui Fang’s group at Dartmouth college and quantified device performance in vitro and in vivo. First, I designed the IC by establishing design requirements informed by neural signal characteristics and spatial constraints. I then investigated different circuit architectures for the front-end recording pixel, optimizing them with respect to noise, power consumption, area efficiency, bandwidth, and post-processing considerations. This optimization process was extended to the peripheral IC components, including digital controls, analog bias circuits, and electrostatic discharge (ESD) protection. Concurrently, I developed the IC layout and a post-processing testing framework and conducted parasitic extraction simulations at multiple hierarchical levels, spanning from the IC’s top level to external recording electronics, to assess performance. The IC shank incorporated 32 electrodes with a 50 μm pitch, delivering 28 dB signal amplification, filtering within a 0.06 Hz–10.04 kHz range, and multiplexing signals in a 32:1 ratio at 10 kSPS per channel. Simulations indicated a low input-referred noise rms of 9.41 ± 1.34 μV in the LFP range (10–200 Hz) and 8.09 ± 1.13 μV in the action potential range (300–3000 Hz), with a power consumption of ~1 μW per pixel. The IC was then fabricated after simulations using a 130-nm silicon-on-insulator (SOI) process from a commercial CMOS foundry. Next, I developed an in vitro testing strategy for both the IC and the transfer-printed IC. I first had the chip die packaged by a third-party company and tested it to assess circuit performance independently of transfer printing. To facilitate this, I designed two PCBs to interface with the packaged chip and programmed a National Instruments (NI) card using MATLAB for signal digitization and digital control. Based on initial results, I developed four additional PCBs to support both the packaged and transfer-printed ICs, as well as future high-channel versions. In vitro testing confirmed that both IC versions closely matched simulations, demonstrating that the circuit function remained intact after transfer printing. Additionally, both successfully recorded artificial neural data in saline at low amplitudes. However, transfer-printed device yield was low, prompting failure analysis and proposed optimizations. This work establishes that (1) large IC regions can be transfer-printed without compromising function, enabling flexible, implantable active devices using industrial foundry ICs, and (2) our circuit architecture supports scalable, high-density, low-noise, low-power, multiplexed recording in vitro. To quantify the performance of the device in vivo, I performed auditory decoding in the rat primary auditory cortex (A1), synchronizing the auditory task with software from the in vitro testing setup and a μECoG system to identify high ESNR regions. The device recorded auditory-evoked responses at various cortical depths, achieving ESNR values up to 13 dB. Neural sources shifted with depth, indicating the ability to track cortical layer populations. Importantly, these findings confirm the device’s capability to record multiplexed neural signals in vivo with ESNR comparable to existing systems. Lastly, I designed a scaled up version of the array through two multi-shank device designs: one with 12 shanks and 384 channels, and another with 16 shanks and 512 channels. I optimized shank pitch and spacer size through 3D modeling and designed a backend connector considering parasitic capacitance and resistance. Simulations showed that parasitics did not significantly impact noise or inter-shank variability. To support high-channel recording, I modified the software to handle up to 512 channels across 16 shanks, advancing scalable neural recording with active devices. This design can be used to create high channel, low noise, multiplexed arrays. In summary, this dissertation presents the development of a scalable, flexible neural interface—achieving a 17× lower bending radius than previous foundry-fabricated CMOS devices—while maintaining low noise (<10 µV), low power consumption (11–20× lower than prior work), small front-end area (5-20 × lower than previous work) and active multiplexing by integrating commercial IC design with transfer printing. This work confirms that large IC regions can be transfer-printed without functional loss, enabling flexible, implantable active devices using industrial foundry ICs. Additionally, the proposed circuit architecture supports scalable, high-density, low-noise, low-power, actively multiplexed recording in vitro and in vivo. Overall, this architecture paves the way for significantly higher channel count neural interfaces and can be adapted broadly across neural interfaces including intracortical and μECoG arrays to improve BCI performance.