Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool
| dc.contributor.advisor | Kim, Jungsang | |
| dc.contributor.author | Ahsan, Muhammad | |
| dc.date.accessioned | 2015-09-01T19:50:43Z | |
| dc.date.available | 2015-09-01T19:50:43Z | |
| dc.date.issued | 2015 | |
| dc.department | Computer Science | |
| dc.description.abstract | The challenge of building scalable quantum computer lies in striking appropriate balance between designing a reliable system architecture from large number of faulty computational resources and improving the physical quality of system components. The detailed investigation of performance variation with physics of the components and the system architecture requires adequate performance simulation tool. In this thesis we demonstrate a software tool capable of (1) mapping and scheduling the quantum circuit on a realistic quantum hardware architecture with physical resource constraints, (2) evaluating the performance metrics such as the execution time and the success probability of the algorithm execution, and (3) analyzing the constituents of these metrics and visualizing resource utilization to identify system components which crucially define the overall performance. Using this versatile tool, we explore vast design space for modular quantum computer architecture based on trapped ions. We find that while success probability is uniformly determined by the fidelity of physical quantum operation, the execution time is a function of system resources invested at various layers of design hierarchy. At physical level, the number of lasers performing quantum gates, impact the latency of the fault-tolerant circuit blocks execution. When these blocks are used to construct meaningful arithmetic circuit such as quantum adders, the number of ancilla qubits for complicated non-clifford gates and entanglement resources to establish long-distance communication channels, become major performance limiting factors. Next, in order to factorize large integers, these adders are assembled into modular exponentiation circuit comprising bulk of Shor's algorithm. At this stage, the overall scaling of resource-constraint performance with the size of problem, describes the effectiveness of chosen design. By matching the resource investment with the pace of advancement in hardware technology, we find optimal designs for different types of quantum adders. Conclusively, we show that 2,048-bit Shor's algorithm can be reliably executed within the resource budget of 1.5 million qubits. | |
| dc.identifier.uri | ||
| dc.subject | Computer science | |
| dc.subject | Electrical engineering | |
| dc.subject | Physics | |
| dc.subject | analysis Shor's algorithm | |
| dc.subject | performance simulation tool | |
| dc.subject | quantum architecture | |
| dc.subject | quantum CAD | |
| dc.subject | quantum computer design space | |
| dc.subject | Quantum computing | |
| dc.title | Architecture Framework for Trapped-ion Quantum Computer based on Performance Simulation Tool | |
| dc.type | Dissertation |