BOLT: Energy-efficient out-of-order latency-tolerant execution

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LT (latency tolerant) execution is an attractive candidate technique for future out-of-order cores. LT defers the forward slices of LLC (last-level cache) misses to a slice buffer and re-executes them when the misses return. An LT core increases ILP without physically scaling the issue queue and register file and increases MLP without additional software threads that can reduce cache performance. Unfortunately, proposed LT designs are not energy ef.cient. They require too many additional structures and they defer and re-execute too many instructions to justify their performance gains. In this paper, we address these inefficiencies. We introduce a microarchitecture called BOLT (Better Out-of-Order Latency-Tolerance) that implements LT as an alternative use of SMT (Simultaneous Multi-Threading). We also present a new slice buffer organization and traversal scheme that increases performance and reduces overhead by pruning instances of useless and redundant LT. Collectively, these modifications turn out-of-order LT into a technique that improves performance in an energy-efficient way. ©2009 IEEE.








Andrew Douglas Hilton

Professor of the Practice in the Department of Electrical and Computer Engineering

Drew Hilton is a Professor of the Practice in Electrical and Computer Engineering, as well as Pratt’s Director of Innovation in Computing Education.

His main focus is on teaching professional-level programming skills to ECE’s master's students to prepare them for software engineering careers.

Professor Hilton also teaches a 3-week introduction to Programming Python for Duke's Master in Interdisciplinary Data Science, and Duke's Center for Computational Thinking.

He has two Coursera specializations, one in Java, and another in C.

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