Efficient Test Methods for RF Transceivers

Advancements of the semiconductor technology opened a new era in

wireless communications which led manufacturers to produce faster,

more functional devices in much smaller sizes. However, testing

these devices of today's technology became much harder and expensive

due to the complexity of the devices and the high operating speeds.

Moreover, testing these devices becomes more important since decreasing

feature sizes increase the probability of parametric and catastrophic

faults because of the severe effects of process variations. Manufacturers

have to increase their test budgets to address quality and reliability

concerns. In the radio frequency (RF) domain, overall test cost are higher

due to equipment costs, test development and test time costs. Advanced

circuit integration, which integrates various analog and digital circuit

blocks into single device, increases test costs further because of the

additional tests requiring new test setups with extra test equipments.

Today's RF transceiver circuits contain many analog and digital circuit

blocks, such as synthesizers, data converters and the analog RF front-end

leading to a mixed signal device. Verification of the specifications and

functionality of each circuit block and the overall transceiver require

RF instrumentation and lengthy test routines. In this dissertation, we

propose efficient component and system level test methods for RF

transceivers which are low cost alternatives to traditional tests.

In the first component level test, we focus on in-band phase noise of the

phase locked loops (PLL). Most on-chip self-test methods for PLLs aim at

measuring the timing jitter that may require precise reference clocks and/or

additional computation of measured specs. We propose a built in test (BiT)

circuit to perform a go/no-go test for in-band PLL phase noise. The proposed

circuit measures the band-limited noise power at the input of the voltage

controlled oscillator (VCO). This noise power is translated as the high

frequency in-band phase noise at the output of the PLL. Our circuit contains

a self calibration sequence based on a simple sinusoidal input signal to make

it robust with respect to process variations.

The second component level test is a built in self test (BiST) scheme

proposed for analog to digital converters (ADC) based on a linear ramp

generator and efficient output analysis. The proposed analysis method is

an alternative to histogram based analysis techniques to provide test time

improvements, especially when the resources are scarce. In addition to the

measurement of differential nonlinearity (DNL) and integral nonlinearity

(INL), non-monotonic behavior of the ADC can also be detected with the

proposed technique. The proposed ramp generator has a high linearity

capable of testing 13-bit ADCs.

In the proposed system level test methods, we utilize the loop-back

configuration to eliminate the need for an RF instrument. The first loop-back

test method, which is proposed for wafer level test of direct conversion

transceivers, targets catastrophic and large parametric faults. The use of

intermediate frequencies (IF) generates a frequency offset between the transmit

and receive paths and prevents a direct loop-back connection. We overcome this

problem by expanding the signal bandwidth through saturating the receive path

composed of low noise amplifier (LNA) and mixer. Once the dynamic range of the

receiver path is determined, complete transceiver can be tested for catastrophic

signal path faults by observing the output signal. A frequency spectrum

envelope signature technique is proposed to detect large parametric faults.

The impact of impairments, such as transmitter receiver in-phase/quadrature

(I/Q) gain and phase mismatches on the performance have become severe due to

high operational speeds and continuous technology scaling. In the second system

level loop-back test method, we present BiST solutions for quadrature modulation

transceiver circuits with quadrature phase shift keying (QPSK) and Gaussian

minimum shift keying (GMSK) baseband modulation schemes. The BiST methods

use only transmitter and receiver baseband signals for test analysis. The

mapping between transmitter input signals and receiver output signals are

used to extract impairment and nonlinearity parameters separately with the

help of signal processing methods and detailed nonlinear system modeling.

The last system level test proposed in this dissertation combines the benefits

of loop-back and multi-site test approaches. In this test method, we present

a 2x-site test solution for RF transceivers. We perform all operations on

communication standard-compliant signal packets, thereby putting the device

under the normal operating conditions. The transmitter on one device under

test (DUT) is coupled with a receiver on another DUT to form a complete TX-RX

path. Parameters of the two devices are decoupled from one another by carefully

modeling the system into a known format and using signal processing techniques.