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Test-Cost Modeling and Optimal Test-Flow Selection of 3D-Stacked ICs

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Date
2015-03-02
Authors
Agrawal, M
Chakrabarty, K
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Abstract
Three-dimensional (3D) integration is an attractive technology platform for next-generation ICs. Despite the benefits offered by 3D integration, test cost remains a major concern, and analysis and tools are needed to understand test flows and minimize test cost.We propose a generic cost model to account for various test costs involved in 3D integration and present a formal representation of the solution space to minimize the overall cost. We present an algorithm based on A*—a best-first search technique—to obtain an optimal solution. An approximation algorithm with provable bounds on optimality is proposed to further reduce the search space. In contrast to prior work, which is based on explicit enumeration of test flows, we adopt a formal optimization approach, which allows us to select an effective test flow by systematically exploring an exponentially large number of candidate test flows. Experimental results highlight the effectiveness of the proposed method. Adopting a formal approach to solving the cost-minimization problem provides useful insights that cannot be derived via selective enumeration of a smaller number of candidate test flows.
Type
Report
Subject
3D chip testing
cost models
test cost
test flows
Permalink
https://hdl.handle.net/10161/9495
Citation
Agrawal, M; & Chakrabarty, K (2015). Test-Cost Modeling and Optimal Test-Flow Selection of 3D-Stacked ICs. Retrieved from https://hdl.handle.net/10161/9495.
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Chakrabarty

Krishnendu Chakrabarty

John Cocke Distinguished Professor of Electrical and Computer Engineering
Krishnendu Chakrabarty is the John Cocke Distinguished Professor of Electrical and Computer Engineering and Professor of Computer Science at Duke University.
This author no longer has a Scholars@Duke profile, so the information shown here reflects their Duke status at the time this item was deposited.

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