Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits

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Timing-related defects are major contributors to test escapes and in-field reliability problems for very-deep submicrometer integrated circuits. Small delay variations induced by crosstalk, process variations, power-supply noise, as well as resistive opens and shorts can potentially cause timing failures in a design, thereby leading to quality and reliability concerns. We present a test-grading technique that uses the method of output deviations for screening small-delay defects (SDDs). A new gate-delay defect probability measure is defined to model delay variations for nanometer technologies. The proposed technique intelligently selects the best set of patterns for SDD detection from an n-detect pattern set generated using timing-unaware automatic test-pattern generation (ATPG). It offers significantly lower computational complexity and excites a larger number of long paths compared to a current generation commercial timing-aware ATPG tool. Our results also show that, for the same pattern count, the selected patterns provide more effective coverage ramp-up than timing-aware ATPG and a recent pattern-selection method for random SDDs potentially caused by resistive shorts, resistive opens, and process variations. © 2010 IEEE.






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Yilmaz, M, K Chakrabarty and M Tehranipoor (2010). Test-pattern selection for screening small-delay defects in very-deep submicrometer integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(5). pp. 760–773. 10.1109/TCAD.2010.2043591 Retrieved from https://hdl.handle.net/10161/1376.

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